By Venktesh Shukla, Chief Executive Officer, Nusym Technology, Inc. Courtesy of EE Times (05/16/2008 2:51 PM EST)

Electronic company executives are writing $1,000,000 checks for the unpredicted expense of device respins in the event of an undiscovered bug, and not getting fired. Why? Because the electronics industry as a whole has been forced to accept the astronomical risks and cost associated with verification of integrated circuits.

The semiconductor industry's ability to deliver new hardware innovations in a timely and cost effective manner is grossly inhibited by the open loop verification process used today. It is becoming inordinately harder to achieve reliable and expedient functional verification closure - this problem has been well understood for over a decade, but attempts to solve it to date have fallen short. An intelligent verification methodology that closes this loop and reunites design insight with verification is required to bring these spiraling verification efforts and costs back under control.

If a bug makes it through fabrication, a post-design investigation will invariably point to verification as the smoking gun. Multiple surveys have pointed out that the overwhelming reason for respins is that design flaws are found too late in the verification process. Given the complexity of modern devices, it is inevitable that bugs will find their way into designs. The job of the verification process is to ensure that these bugs are stamped out before they can do harm. Project managers are painfully aware of the importance of effective verification, which has gone from a small component of overall design in the 1980s to 70% or more of overall implementation effort today. Large teams of verification specialists hurl vast numbers of tests at design descriptions, looking at every scenario detailed in the specification. Today there is no way to ascertain whether a design has been fully verified with 100% confidence.

In the 1980s the smaller designs were verified by the designers who had an understanding of the code structure, and were able to direct tests to specific areas, making sure that all of their code was checked out. In the 1990s, as design size and complexity exploded, the use of constrained random test generation by separate verification teams gained in acceptance. This new verification approach had major advantages in terms of the generation of vast numbers of tests based directly on the design specification. However, it was flawed in that insight in design was no longer part of the verification equation, which directly impacted time and resources needed to develop confidence in the design.

Many approaches included coverage analysis mechanisms to provide metrics of verification quality, but these could never replace the confidence instilled by design engineers creating directed tests based on their knowledge of the design structure. The result is that companies can currently achieve 70-80% coverage with reasonable effort, but it takes an enormous investment of time and resources to improve beyond that. Without proper control on test direction, the entire verification process runs as an open-loop, leading to a massive redundancy in applied tests that require large engineering teams to create, and massive simulation computer "farms" to apply. Simulation is fundamentally running out of control " the entire industry must figure out a way to reign in this budget-blowing task and unpredictable respins.

What is needed is an "intelligent verification" methodology, which brings back design insight to accelerate the verification process. The "intelligence" will ensure that simulation cycles are not wasted in verifying something that has already been verified and that the shortest path is being taken to reach bugs. This intelligent verification would meet the following key goals in electronic design today - increasing verification confidence automatically, tracking hard to reach design areas, and eliminating test redundancy - while scaling to large designs and requiring minimal change in current verification methodologies.

Acting in much the same way as a designer but leveraging the automation necessary to cope with today's huge designs, intelligent verification is critical to moving us toward the holy grail of verification: verification closure at a fraction of time and resources it takes today. Reducing the risk associated with the creation of hardware devices by increasing its verification confidence and efficiency would have a major positive impact on the health and continued innovation of the entire electronics industry.