DFM in itself is a simple premise based on the idea that designers should make "ease of manufacturing" a main consideration in the product development process. In fact, DFM is now one of the hottest topics in the semiconductor industry, as it is greatly needed in such advanced technology generations as 90-, 65- and 45-nanometer manufacturing.

With the proliferation of complex nanometer technologies and the growing sophistication of SoC designs, manufacturing can no longer be considered an afterthought, particularly as there is more opportunity for variations in the nanometer silicon design and manufacturing cycle.

Applying a DFM methodology for 90 nm and below enables manufacturing variations to be included in models, where they can be predicted and thus compen-

sated for. By deploying DFM, companies can lessen the sensitivity of their designs to manufacturing variations and effectively address yield- and performance-diminishing issues at the design stage.

More DFM and electronic design automation (EDA) vendors are working to develop DFM solutions. Semiconductor foundries are also taking an important role in DFM product developments. Leading foundries are providing solutions to make SoC designs more manufacturable in terms of improved yield, accelerated time-to- market, and shorter volume production ramp-up time.

These DFM benefits translate into faster time-to-profit across the supply chain, specifically for foundry customers, who must compete in a digital world where competition is fierce and rapid market saturation for new products is the rule.

A number of relatively new DFM solutions bring manufacturing awareness into customers' design environments. These include:

• Modeling systematic variations, such as well-proximity effects, length of diffusion effects and wire edge effects (WEE),

• Building in Monte Carlo Spice models,

• Providing necessary guidelines, libraries and tools,

• Facilitating a seamless design flow with the traditional flow by means of compliant libraries, enhanced rule and deck files, yield enhancement models and statistical static timing analysis (SSTA).

Comprehensive DFM solutions
Before executing DFM, SoC designers should take a good look at their foundries' DFM offerings. DFM portfolios available from foundries should include models to predict such second-order effects as length of diffusion, well proximity effect and chemical-mechanical polishing (CMP) effects.

To address physical-design concerns, design rule manuals should address all DFM recommended rules that can be applied by layout designers. Foundries should also offer dummy fill and metal slotting when needed after the GDS2 (graphic data systems) files are received. Finding a foundry that offers a lithography simulation check service or tools support to detect potential hot spots is also recommended.

With this approach, designers have the opportunity to revise layout patterns to make them optical proximity correction friendly. Finally, critical-area analysis is recommended for identifying open/short/bridge locations so designers can remove these risky areas. These models and analyses should be incorporated into the existing flow, which is familiar to the designers. For design implementation, foundries such as UMC provide script files to perform double via insertion, limit via stacking (script files available for both via procedures), and do wire spreading and widening.

Design reference flows provide a road map to successful tapeout. In fact, most foundries provide silicon-validated reference design flows that demonstrate a methodology to provide designers with a quick start or point of reference when establishing an in-house IC design flow. For technologies at 90 nm and below, foundries often incorporate the latest DFM capabilities into the flow.

When performing DFM-compliant design with DFM recommendation rules, it's important to find an offering that reduces hard-failure probability through the use of such techniques as double-via insertion and limiting the number of stacked vias. Another priority is to reduce device variation through recommendation rules of poly1 gate pitch, diffusion width, contact enclosure and spacing, etc. Another goal is to reduce the frequency of critical area and feature to boost yield ramp-up.

DFM in the EDA flow
Manufacturing knowledge is brought forward through DFM solutions integrated with EDA tools. For example, in logic synthesis, DFM-compliant standard cells consisting of process-optimized GDS2 patterns and timing characterization are available.

During the place and route stage, such DFM information as compliant metal routing, wire spreading and timing-driven metal fill is available, as are such DFM optimization techniques as double-via insertion and limit via stack. This is followed by parasitic extraction, at which stage such select foundries as UMC incorporate accurate timing extraction with embedded modeling for both WEEs and CMP effects.

DFM analysis of GDS2 subsequently takes place, using litho simulation to identify potential hot spots and critical-area analysis utilizing defect data embedded technology files. At the end, the timing analysis will be enhanced by tighter corner margining through statistical models by SSTA-aware timing tools.

Foundries began accelerating the incorporation of DFM methodologies into the tapeout flow because of soaring costs, the desire to help customers avoid silicon respins and the increased complexity of designing into nanometer technologies. It became of utmost importance for foundries to help designers achieve first-time-right silicon and a fast-yield-ramping product. For example, UMC began in earnest at the 0.13-micron node with the incorporation of Monte Carlo models, DFM rules and WEE models. It improved on this foundation at 90 nm by adding WPE and LOD modeling, while making statistical timing analysis, critical-area analysis, CMP modeling and litho simulation checks available at 65 nm. Electrical DFM and restricted rules are the next DFM tools to be available.

A luxury at one time, DFM solutions are now a necessity for designers to succeed in today's ultracompetitive environment. DFM players, EDA vendors and foundries have introduced a range of DFM techniques. Foundry solutions include DFM guidelines, relevant technology files to implement required rules, scripts for double-via insertion and stack via checks, DFM-aware standard cells, relevant EDA tools support, postlayout litho simulation check service and design-for-diagnostics services for designs with scan chain.

These embedded DFM resources are lessening the burden and challenges of designing into today's most advanced process technology, enabling designers to focus on creating market-winning products. As a result, DFM is no longer the methodology of the future but one that is critical to SoC development and, thus, a methodology that is here to stay.

Patrick T. Lin is chief SoC architect/system and architecture support at United Micro- electronics Corp. Contact him at patrick.t.lin@umc-usa.com.