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Tezzaron delivers challenge to SRAM, DRAM Says its new CMOS-based pseudo-static memory is faster
The company, based in Naperville, Ill., claims its PSiRAM is one of the world's fastest memory devices. A 32Mbit prototype chip fabricated in 90nm CMOS boasts 1.3ns latency, 1ns cycle time, and 400MHz performance in a 2Mbit ¥ 16-bit quad-data-rate configuration. Fabless Tezzaron--formerly known as Tachyon Semiconductor-- has offered a variety of technologies and services, including 3-D wafer-stacking, ferroelectric process technology, built-in self-test tools, microcontroller IP, and design. The new pseudo-SRAM cell represents yet another dimension of its product strategy. The PSiRAM is targeted for implementation in 130- and 90nm processes. The underlying technology is a patented three-transistor cell, which senses changes in electrical current rather than measuring electrical voltage. The decision to sense current change rather than voltage not only reduces the read delay, it eliminates the turnaround time on read-modify-write cycles, vastly improving throughput on some types of operations, according to Bob Patti, Tezzaron's chief technology officer. "We will provide two versions of the part," Patti said. "One will have completely hidden refresh, and thus appear as a standard SRAM. The other will require user refresh much like DRAM does today. The DRAM version will run faster than the SRAM version. The SRAM part would have a latency of [around] 1.8ns instead of 1.3ns." Because everything in the PSiRAM process is CMOS-compatible, the company also plans to license the technology for use as embedded memory in SoCs. In both embedded and discrete applications the array is said to require one half the area of an equivalent SRAM. Tezzaron plans volume production of PSiRAM chips next year. A 130nm version is slated for the first half of 2004, and a 90nm version late next year.
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