By Don Scansen EE Times (09/14/2009 7:57 PM EST)

OTTAWA — I recently had another chance to hear Intel Senior Fellow Mark Bohr present highlights of the company's latest process technology.

As if it wasn't enough to hear about process development directly from an Intel engineer who has been there through the transition from metal to poly gates and back again, this time I also was fortunate to have Sanjay Natarajan on hand to add details and answer my questions. Natarajan is Intel's 32-nm program manager charged with keeping his node rolling ahead of schedule.

The latest Intel briefing provided some news in advance of the 2009 Intel Developer Forum (IDF) beginning Sept. 22 in San Francisco. I expect Intel will announce the launch or at least the launch date for the first chips from the Westmere 32-nm family of processors during IDF.

Intel's PR team had two more reasons for holding analyst calls last week. One was to announce two papers that will be presented at IEDM in December. The second, but more significant, is that 32-nm production wafers are now moving through Intel's D1D fab in Oregon.

I have not yet deciphered the code for what is happening here, but these wafers are said to be "in support of planned Q4 revenue production." If you take that at face value, then Intel should be shipping 32-nm processors to customers before the end of the year.

However, none of the people I talked to at Intel were willing to commit to that deadline despite widespread assumptions that they will. That's why I suspect important announcements will be made next week since there is no reason to believe product shipments would be delayed at this point.

One IEDM papers describes the 32-nm process which is Intel's second generation of high-k metal gate (HKMG) technology. Paul Packan will present "32-nm Technology for High Performance CPUs." Natarajan said Intel's presentation will provide more process details than past conference papers.

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